Aspects and embodiments of the invention pertain to time delay apparatus, methods, and applications thereof; more particularly to CMOS integrated time delay apparatus, methods, and applications thereof; and, most particularly to a CMOS integrated, temperature-compensated, ultrasonic-based time delay apparatus, methods, and applications.
Delay lines (blocks) are ubiquitous in the field of electronics. A delay block is a circuit that shifts the input signal in time by a desired amount, and delivers a delayed output similar to the input signal. Delay elements can be used in wide range of applications including phase modulation in clocking systems, generating stable clocks in digital systems, and RF signal correlation processing. Furthermore, stable delay elements can be used as a timing reference in delay-locked-loops where the delay can be calibrated across different temperature and process variations. Precision and stability in a delay element block is one of the key specifications that directly impacts all the applications.
Different architectures for on-chip delay elements have been reported in the literature. The most commonly used delay method is an inverter-based delay line where the delay is proportional to the number of inverter buffers multiplied by the delay of a single buffer. This architecture is sensitive to process and temperature variations as well as supply voltage fluctuations. RC delay elements are also widely used in different delay-based applications, however, this approach also suffers from high temperature dependence (2500 ppm/° C.). In a reported thyristor-based delay element, the delay is proportional to the current source as well as the threshold voltage of CMOS transistors, thus minimizing the supply dependence and hence enhancing the supply noise rejection. Minimum delay variation to power supply noise of 9.43% was reported with 314 ppm/° C. temperature coefficient. Known surface acoustic wave (SAW)-based and optical delay lines, while less temperature sensitive are difficult to integrate on CMOS with high (long) delay values.
A solution to low stability, achieving longer delay time, control of temperature sensitivity, and creating the compatibility to CMOS integration is provided by the embodied invention in the form of a CMOS compatible pulse/echo transmit-receive ultrasonic delay element that is stable over time to less than 6 ppm and has a zero temperature coefficient of delay at two temperatures.